ARM Cortex-A53

ARM Cortex-A53
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General information
Launched2012
Designed byARM Holdings
Performance
Max. CPU clock rate400 MHz  to 2.30 GHz 
FSB speeds100 MHz  to 118 MHz OC 
Cache
L1 cache8–64 KiB
L2 cache128 KiB  2 MiB
Architecture and classification
Instruction setARMv8-A
Physical specifications
Cores
  • 1–8 per cluster
Products, models, variants
Product code name
  • Apollo
History
PredecessorARM Cortex-A7
SuccessorARM Cortex-A55

The ARM Cortex-A53 is one of the first two central processing units implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre, along with the Cortex-A57. The Cortex-A53 is a 2-wide decode superscalar processor, capable of dual-issuing some instructions.[1] It was announced October 30, 2012[2] and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration. It is available as an IP core to licensees, like other ARM intellectual property and processor designs.

  1. ^ "Cortex-A53 Processor". ARM Holdings. Retrieved 2015-11-08.
  2. ^ "ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors" (Press release). ARM Holdings. 2012-10-30. Retrieved 2023-05-15.

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