Back ARM Cortex-A73 Catalan ARM Cortex-A73 French ARM Cortex-A73 Hungarian ARM Cortex-A73 Ukrainian ARM Cortex-A73 Chinese
| General information | |
|---|---|
| Launched | 2016 |
| Designed by | ARM Holdings |
| Max. CPU clock rate | to 2.8 GHz |
| Cache | |
| L1 cache | 96–128 KiB (64 KiB I-cache with parity, 32–64 KiB D-cache) per core |
| L2 cache | 1–8 MiB |
| L3 cache | None |
| Architecture and classification | |
| Application | Mobile |
| Instruction set | ARMv8-A |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code name |
|
| History | |
| Predecessors | ARM Cortex-A72 ARM Cortex-A17 |
| Successor | ARM Cortex-A75 |
The ARM Cortex-A73 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Sophia design centre. The Cortex-A73 is a 2-wide decode out-of-order superscalar pipeline.[1] The Cortex-A73 serves as the successor of the Cortex-A72, designed to offer 30% greater performance or 30% increased power efficiency.[2]
- ^ "Cortex-A73 Processor". ARM Holdings. Retrieved 2017-03-28.
- ^ Cutress, Ian; Tallis, Billy (29 May 2016). "Computex 2016: ARM Press Conference Live Blog". Anandtech. Retrieved 29 March 2017.