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Double data rate

A comparison between single data rate, double data rate, and quad data rate. The dots are where data transfers take place, measured in millions of transfers per second (MT/s).

In computing, double data rate (DDR) describes a computer bus that transfers data on both the rising and falling edges of the clock signal and hence doubles the memory bandwidth by transferring data twice per clock cycle.[1][2][3] This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used in the context of NAND flash memory.

  1. ^ Hennessy, John L.; Patterson, David A. (2007). Computer architecture: a quantitative approach. Amsterdam: Morgan Kaufmann. p. 314. ISBN 978-0-12-370490-0.
  2. ^ Harris, Sarah L.; Harris, David Money (2016). "I/O Systems: 9.6.3 DDR3 Memory". Digital Design and Computer Architecture. Elsevier. p. 531.e1–531.e64. doi:10.1016/b978-0-12-800056-4.00015-7. ISBN 978-0-12-800056-4. DRAM connects to the microprocessor over a parallel bus. In 2015, the present standard is DDR3, a third generation of double-data rate memory bus operating at 1.5 V. Typical motherboards now come with two DDR3 channels so they can simultaneously access two banks of memory modules. DDR4 is ... operating at 1.2V ...
  3. ^ "double data rate (DDR) Definition". Intel. Retrieved 2024-04-07.

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