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The MESI protocol is an Invalidate-based cache coherence protocol, and is one of the most common protocols that support write-back caches. It is also known as the Illinois protocol due to its development at the University of Illinois at Urbana-Champaign.[1] Write back caches can save considerable bandwidth generally wasted on a write through cache. There is always a dirty state present in write-back caches that indicates that the data in the cache is different from that in the main memory. The Illinois Protocol requires a cache-to-cache transfer on a miss if the block resides in another cache. This protocol reduces the number of main memory transactions with respect to the MSI protocol. This marks a significant improvement in performance.[2]
- ^ Papamarcos, M. S.; Patel, J. H. (1984). "A low-overhead coherence solution for multiprocessors with private cache memories" (PDF). Proceedings of the 11th annual international symposium on Computer architecture - ISCA '84. p. 348. doi:10.1145/800015.808204. ISBN 0818605383. S2CID 195848872. Retrieved March 19, 2013.
- ^ Gómez-Luna, J.; Herruzo, E.; Benavides, J.I. "MESI Cache Coherence Simulator for Teaching Purposes". Clei Electronic Journal. 12 (1, PAPER 5, APRIL 2009). CiteSeerX 10.1.1.590.6891.