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MIPS architecture

MIPS
DesignerMIPS Technologies, Imagination Technologies
Bits64-bit (32 → 64)
Introduced1985 (1985)
VersionMIPS32/64 Release 6 (2014)
DesignRISC
TypeLoad–store
EncodingFixed
BranchingCompare and branch, with a 1 instruction delay after the branching condition check
EndiannessBi
Page size4 KB
ExtensionsMDMX, MIPS-3D
OpenPartly. The R16000 processor has been on the market for more than 20 years and as such cannot be subject to patent claims. Therefore, the R16000 and older processors are fully open.
Registers
General-purpose32
Floating point32

MIPS (Microprocessor without Interlocked Pipelined Stages)[1] is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)[2]: A-1 [3]: 19  developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6.[4][5] MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.

The MIPS architecture has several optional extensions: MIPS-3D, a simple set of floating-point SIMD instructions dedicated to common 3D tasks;[6] MDMX (MaDMaX), a more extensive integer SIMD instruction set using 64-bit floating-point registers; MIPS16e, which adds compression to the instruction stream to reduce the space programs take up;[7] and MIPS MT, which adds multithreading capability.[8]

Computer architecture courses in universities and technical schools often study the MIPS architecture.[9] The architecture greatly influenced later RISC architectures such as Alpha. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to RISC-V.[10]

  1. ^ Patterson, David (2014). Computer Organization and Design (PDF). Elsevier. pp. 4.16–4. ISBN 978-0-12-407726-3. Archived (PDF) from the original on September 4, 2019. Retrieved November 28, 2018.
  2. ^ Price, Charles (September 1995). MIPS IV Instruction Set (Revision 3.2), MIPS Technologies, Inc.
  3. ^ Sweetman, Dominic (1999). See MIPS Run. Morgan Kaufmann Publishers, Inc. ISBN 1-55860-410-3.
  4. ^ "MIPS32 Architecture". MIPS. Archived from the original on March 21, 2020. Retrieved March 20, 2020.
  5. ^ "MIPS64 Architecture". MIPS. Archived from the original on February 2, 2020. Retrieved March 20, 2020.
  6. ^ "MIPS-3D ASE". Imagination Technologies. Archived from the original on January 3, 2014. Retrieved January 4, 2014.
  7. ^ "MIPS16e". MIPS. Archived from the original on January 16, 2021. Retrieved March 20, 2020.
  8. ^ "MIPS Multithreading". MIPS. Archived from the original on October 26, 2020. Retrieved March 20, 2020.
  9. ^ University of California, Davis. "ECS 142 (Compilers) References & Tools page". Archived from the original on March 21, 2011. Retrieved May 28, 2009.
  10. ^ Turley, Jim (March 8, 2021). "Wait, What? MIPS Becomes RISC-V". Electronic Engineering Journal. Archived from the original on March 21, 2021. Retrieved March 28, 2021.

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