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Multiple patterning

Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.

Different techniques for multiple patterning
Top: Splitting of features into groups (3 shown here), each patterned by a different mask
Center: Use of a spacer to generate additional separate features in the gaps
Bottom: Use of an opposite polarity feature to cut (small break) pre-existing features

Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by Intel for line-cutting at its 45nm node[1] or TSMC at its 28nm node.[2] Even for electron-beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.[3][4]

Double patterning lithography was first demonstrated in 1983 by D. C. Flanders and N. N. Efremow.[5] Since then several double patterning techniques have been developed such as self alignment double patterning (SADP) and a litho-only approach to double patterning.[6][7]

Pitch double-patterning was pioneered by Gurtej Singh Sandhu of Micron Technology during the 2000s, leading to the development of 30-nm class NAND flash memory. Multi-patterning has since been widely adopted by NAND flash and random-access memory manufacturers worldwide.[8][9]

  1. ^ Intel 45nm HKMG
  2. ^ TSMC 28nm cutpoly
  3. ^ Chao, Weilun; Kim, Jihoon; Anderson, Erik H.; Fischer, Peter; Rekawa, Senajith; Attwood, David T. (2009-01-09). Double patterning HSQ processes of zone plates for 10 nm diffraction limited performance. The 53rd International Symposium on Electron, Ion, and Photon Beams and Nanolithography, Marco Island, FL, May 26–29, 2009.
  4. ^ Duan, Huigao; Winston, Donald; Yang, Joel K. W.; Cord, Bryan M.; Manfrinato, Vitor R.; Berggren, Karl K. (November 2010). "Sub-10-nm half-pitch electron-beam lithography by using poly(methyl methacrylate) as a negative resist" (PDF). Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28 (6): C6C58–C6C62. Bibcode:2010JVSTB..28C..58D. doi:10.1116/1.3501353. hdl:1721.1/73447. Archived from the original (PDF) on 2012-01-19.
  5. ^ D. C. Flanders; N. N. Efremow (1983). "Generation of <50 nm period gratings using edge defined techniques". Journal of Vacuum Science & Technology B. 1 (4): 1105–1108. Bibcode:1983JVSTB...1.1105F. doi:10.1116/1.582643.
  6. ^ Chris Bencher; Yongmei Chen; Huixiong Dai; Warren Montgomery; Lior Huli (2008). "22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)". Optical Microlithography XXI. 6924. Optical Microlithography XXI; 69244E: 69244E. Bibcode:2008SPIE.6924E..4EB. doi:10.1117/12.772953. S2CID 121968664.
  7. ^ A. Vanleenhove; D. Van Steenwinckel (2007). Flagello, Donis G (ed.). "A litho-only approach to double patterning". Society of Photo-Optical Instrumentation Engineers (Spie) Conference Series. Optical Microlithography XX. 6520. Optical Microlithography XX; 65202F: 65202F. Bibcode:2007SPIE.6520E..2FV. doi:10.1117/12.713914. S2CID 119829809.
  8. ^ "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Archived from the original on September 9, 2018. Retrieved 4 July 2019.
  9. ^ "Micron Named Among Top 100 Global Innovators for Sixth Straight Year". Micron Technology. 2018-02-15. Retrieved 5 July 2019.

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