Network on a chip

A network on a chip or network-on-chip (NoC /ˌɛnˌoʊˈsiː/ en-oh-SEE or /nɒk/ knock)^{[nb 1]} is a network-based communications subsystem on an integrated circuit ("microchip"), most typically between modules in a system on a chip (SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system, and are designed to be modular in the sense of network science. The network on chip is a router-based packet switching network between SoC modules.

NoC technology applies the theory and methods of computer networking to on-chip communication and brings notable improvements over conventional bus and crossbar communication architectures. Networks-on-chip come in many network topologies, many of which are still experimental as of 2018. ^{[citation needed]}

In 2000s, researchers had started to propose a type of on-chip interconnection in the form of packet switching networks^[1] in order to address the scalability issues of bus-based design. Preceding researches proposed the design that routes data packets instead of routing the wires.^[2] Then, the concept of "network on chips" was proposed in 2002.^[3] NoCs improve the scalability of systems-on-chip and the power efficiency of complex SoCs compared to other communication subsystem designs. They are an emerging technology, with projections for large growth in the near future as multicore computer architectures become more common.

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^ Guerrier, P.; Greiner, A. (2000). "A generic architecture for on-chip packet-switched interconnections". Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537). Paris, France: IEEE Comput. Soc. pp. 250–256. doi:10.1109/DATE.2000.840047. ISBN 978-0-7695-0537-4. Archived from the original on 2022-10-22. Retrieved 2022-11-23.
^ Proceedings, 2001 Design Automation Conference : 38th DAC: Las Vegas Convention Center, Las Vegas, NV, June 18-22, 2001. Association for Computing Machinery, ACM Special Interest Group on Design Automation. New York, N.Y.: Association for Computing Machinery. 2001. ISBN 1-58113-297-2. OCLC 326240184.{{cite book}}: CS1 maint: others (link)
^ Benini, L.; De Micheli, G. (January 2002). "Networks on chips: a new SoC paradigm". Computer. 35 (1): 70–78. doi:10.1109/2.976921. Archived from the original on 2022-10-22. Retrieved 2022-11-23.

[2] Guerrier, P.; Greiner, A. (2000). "A generic architecture for on-chip packet-switched interconnections". Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537). Paris, France: IEEE Comput. Soc. pp. 250–256. doi:10.1109/DATE.2000.840047. ISBN 978-0-7695-0537-4. Archived from the original on 2022-10-22. Retrieved 2022-11-23.

[3] Proceedings, 2001 Design Automation Conference : 38th DAC: Las Vegas Convention Center, Las Vegas, NV, June 18-22, 2001. Association for Computing Machinery, ACM Special Interest Group on Design Automation. New York, N.Y.: Association for Computing Machinery. 2001. ISBN 1-58113-297-2. OCLC 326240184.{{cite book}}: CS1 maint: others (link)

[4] Benini, L.; De Micheli, G. (January 2002). "Networks on chips: a new SoC paradigm". Computer. 35 (1): 70–78. doi:10.1109/2.976921. Archived from the original on 2022-10-22. Retrieved 2022-11-23.

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