 | This article includes a list of references, related reading, or external links, but its sources remain unclear because it lacks inline citations. (September 2017) |
| POWER, PowerPC, and Power ISA architectures |
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| NXP (formerly Freescale and Motorola) |
| IBM |
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| IBM/Nintendo |
| Other |
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| Cancelled in gray, historic in italic |
The PowerPC e500 is a 32-bit microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03.[citation needed] It has a dual issue, seven-stage pipeline with FPUs (from version 2 onwards), 32/32 KiB data and instruction L1 caches and 256, 512 or 1024 KiB L2 frontside cache. Speeds range from 533 MHz up to 1.5 GHz, and the core is designed to be highly configurable and meet the specific needs of embedded applications with features like multi-core operation interface for auxiliary application processing units (APU).
e500 powers the high-performance PowerQUICC III system on a chip (SoC) network processors and they all share a common naming scheme, MPC85xx. Freescale's new QorIQ is the evolutionary step from PowerQUICC III and will also be based on e500 cores.