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RISC-V

RISC-V
DesignerUniversity of California, Berkeley
Bits32, 64, 128
Introduced6 August 2014 (2014-08-06)[1]
Version
  • unprivileged ISA 20191213,[2]
  • privileged ISA 20211203[3]
DesignRISC
TypeLoad–store
EncodingVariable
BranchingCompare-and-branch
EndiannessLittle[2]: 9 [a]
Page size4 KiB
Extensions
  • M: Multiplication
  • A: Atomics – LR/SC & fetch-and-op
  • F: Floating point (32-bit)
  • D: FP Double (64-bit)
  • Q: FP Quad (128-bit)
  • Zicsr: Control and status register support
  • Zifencei: Load/store fence
  • C: Compressed instructions (16-bit)
  • J: Interpreted or JIT-compiled languages support
OpenYes, royalty free
Registers
General-purpose
  • 16
  • 32
(Includes one always-zero register)
Floating point
  • 32
(Optional. Width depends on available extensions)

RISC-V[b] (pronounced "risk-five"[2]: 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, transferred to the RISC-V Foundation in 2015, and on to RISC-V International, a Swiss non-profit entity, in November 2019.[5][6] Like several other RISC ISAs, e.g. Amber (ARMv2) or OpenRISC, RISC-V is offered under royalty-free open-source licenses.[7] The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD License.

Mainline support for RISC-V was added to the Linux 5.17 kernel, in 2022, along with its toolchain.[8] In July 2023, RISC-V, in its 64-bit variant called riscv64,[9] was included as an official architecture of Linux distribution Debian, in its unstable version.[10] The goal of this project was "to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA."[11]

Some RISC-V International members, such as SiFive, Andes Technology, Synopsys, Alibaba's Damo Academy, Raspberry Pi, and Akeana,[12][13] are offering or have announced commercial systems on a chip (SoCs) that incorporate one or more RISC-V compatible CPU cores.[14]

  1. ^ Asanović, Krste; Patterson, David A. (6 August 2014). Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146.
  2. ^ a b c d Cite error: The named reference isa20191213 was invoked but never defined (see the help page).
  3. ^ Cite error: The named reference priv-isa was invoked but never defined (see the help page).
  4. ^ Urquhart, Roddy (29 March 2021). "What Does RISC-V Stand For? A brief history of the open ISA". Systems & Design: Opinion. Semiconductor Engineering.
  5. ^ "About RISC-V". RISC-V International.
  6. ^ "RISC-V To Move HQ to Switzerland Amid Trade War Concerns". EE Times Europe. 28 November 2019.
  7. ^ "Frequently Asked Questions (FAQ) – RISC-V International". Retrieved 20 August 2024.
  8. ^ "Linux 5.17 Adds Support For "The First Usable, Low-Cost RISC-V Platform" | Michael Larabel, Phoronix – RISC-V International". 2022. Retrieved 20 August 2024.
  9. ^ "RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.
  10. ^ "riscv64 is now an official architecture". lists.debian.org. Retrieved 13 August 2024.
  11. ^ "RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.
  12. ^ Anton Shilov (20 March 2024). "Alibaba claims it will launch a server-grade RISC-V processor this year". Tom's Hardware. Retrieved 19 August 2024.
  13. ^ Connatser, Matthew (13 August 2024). "Akeana debuts RISC-V CPU designs on $100M budget, longs for an Arm wrestle". The Register. Retrieved 19 August 2024.
  14. ^ Cite error: The named reference :5 was invoked but never defined (see the help page).


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